tag:blogger.com,1999:blog-4965561845650139342.post580390875017765772..comments2022-04-04T08:02:59.030-07:00Comments on Digital Logic RTL and Verilog Interview Questions: Write Verilog code to design a digital circuit that generates the Fibonacci seriesUnknownnoreply@blogger.comBlogger3125tag:blogger.com,1999:blog-4965561845650139342.post-64847264620924289132022-04-04T08:02:59.030-07:002022-04-04T08:02:59.030-07:00Hi,
Could you please turn on " contact us &q...Hi,<br /><br />Could you please turn on " contact us "page on ?<br />I had some questions I wanted to ask. <br /><br />Thanks!Anonymoushttps://www.blogger.com/profile/03654414268092263194noreply@blogger.comtag:blogger.com,1999:blog-4965561845650139342.post-52225704321701634762022-03-17T14:47:27.578-07:002022-03-17T14:47:27.578-07:00module fib(input [5:0]N,output reg [5:0]f1,f2,outp...module fib(input [5:0]N,output reg [5:0]f1,f2,output reg [5:0]f3);<br />integer i;<br />always@(N)<br />begin<br />if(N>1)<br />begin<br />f1=0;<br />f2=1;<br /> f3=f1+f2;<br />$display("f3=%d",f3);<br />for(i=0;i<=N;i=i+1)<br />begin<br />$display("f3=%d",f3);<br /> f1=f2;<br /> f2=f3;<br />f3=f1+f2;<br />end <br />end<br />end<br />endmodule<br /><br />module test;<br />wire[5:0]f1,f2,f3;<br />reg [5:0]N;<br />fib fib1(.N(N),.f1(f1),.f2(f2),.f3(f3));<br />initial<br />begin<br /><br />N=5;<br />end<br />endmodule<br /><br /><br /><br />"change the N value based on how many numbers you want in a sequence"Anonymoushttps://www.blogger.com/profile/16287326343597551528noreply@blogger.comtag:blogger.com,1999:blog-4965561845650139342.post-43088116858395479462016-11-06T22:44:57.106-08:002016-11-06T22:44:57.106-08:00yea we need code but not in image format ........
...yea we need code but not in image format ........<br />ps:text formatetwrterwtretwerhttps://www.blogger.com/profile/14042834714385056137noreply@blogger.com