*enable*input signal, which would control if the circuit should advance and calculate the next number in the sequence , or hold its previous value.

**Solution**:

Since the circuit itself must self generate the next number in the sequence, the design must be able to hold the first two starting numbers in the sequence using 2 registers, and they should be reset respectively to 0 and 1.

Below is the block level diagram which contains two registers to hold the current number and the next number in the sequence. There is also control logic for the enable signal which when asserted, the output of the two flops are added together and then the result is stored in the next number register (on that same cycle the next number register shifts into the current number register). When the enable signal is low, the registers hold their previous value.

Below is the Verilog code:

Digital Logic RTL & Verilog Interview Questions |

## 3 Comments

yea we need code but not in image format ........

ReplyDeleteps:text format

module fib(input [5:0]N,output reg [5:0]f1,f2,output reg [5:0]f3);

ReplyDeleteinteger i;

always@(N)

begin

if(N>1)

begin

f1=0;

f2=1;

f3=f1+f2;

$display("f3=%d",f3);

for(i=0;i<=N;i=i+1)

begin

$display("f3=%d",f3);

f1=f2;

f2=f3;

f3=f1+f2;

end

end

end

endmodule

module test;

wire[5:0]f1,f2,f3;

reg [5:0]N;

fib fib1(.N(N),.f1(f1),.f2(f2),.f3(f3));

initial

begin

N=5;

end

endmodule

"change the N value based on how many numbers you want in a sequence"

Hi,

ReplyDeleteCould you please turn on " contact us "page on ?

I had some questions I wanted to ask.

Thanks!