Write Verilog Code to generate Gray Code

   A simple and common interview question for digital designers is to write Verilog code to generate Gray Code.   I’ve seen two ways to accomplish this.  The first method is converting the binary counter to Gray Code using a case statement.   However, there is an easier method, a more general use method that you should be aware of also.

   For example, below is RTL code to convert a 3bit binary counter to a Gray Code counter:

   A 3-bit register binary counter is incremented by 1 each clock cycle.   A signal named “gray_output” decodes the binary counter and then generates the new gray code output. 

   The problem with this approach is that for a Nbit
counter you need to explicitly decode each state. A better, more generic solution using an XOR gate is presented below:

   This was just one question of over 50 questions that are in the Digital Logic RTL & Verilog Interview Questions Book.   The book contains 41figures and drawings, and 28 pratical Verilog code examples.
Digital Logic RTL & Verilog Interview Questions
 You can purchase the Paperback book on Amazon or purchase the PDF E-Book version directly from us on our purchase page.


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