Book Errata

While we make our best attempts at finding all the book errors before it is published, sometimes bugs just slip through (just like in a real circuit design).

Below is a list of errors that were fixed with the latest publication of the book (rev 1.2).   The errors below exist in rev 1.0, 1.1a, and 1.1b.

Question #10
Write Verilog code to capture the input below with a latch and a flip fop, and draw the timing outputs of each:





The Verilog code in the original answer is correct.   However, the timing diagram output of the latch and the flip flop was not.   It should look like this:









Did you find incorrect information in the book?   If so, file a comment below

3 Comments

  1. UnknownJuly 19, 2016 at 2:10 AM

    Page 96, the table at the top. Door 2 column, "This does does not lead to freedom", should be "This door does not lead to freedom"

    ReplyDelete
  2. A Verilog UserAugust 25, 2016 at 3:06 PM

    The e-book I downloaded says version 1.0. Is this correct? This page says that there is a version 1.2.

    ReplyDelete
  3. AmirSeptember 12, 2018 at 9:20 AM

    Page 40 Revision 1.3 August 2015, regarding the generate FIFO signals which written as:

    assign fifo_full = (fifo_count == 8’b1111_1111) ? 1’b1 : 1’b0;
    assign fifo_empty = (fifo_count == 8’b1111_1111) ? 1’b1 : 1’b0;

    This is not true for fifo_empty. The fifo_empty should check if the fifo_count is all '0's:

    assign fifo_full = (fifo_count == 8’b1111_1111) ? 1’b1 : 1’b0;
    assign fifo_empty = (fifo_count == 8’0000_0000) ? 1’b1 : 1’b0;

    ReplyDelete